This invention relates to a semiconductor device having an Si chip mounted on a wiring substrate in a face down manner by way of noble metal bumps and a mounting method thereof and, more particularly, it relate to a chip/substrate bonding structure, a metallized constitution of bonding terminals and a metal bonding method capable of reducing chip damages upon mounting and greatly improving the heat resistance, the temperature cycle life, as well as high temperature-high humidity and high temperature maintaining reliability.
Existent flip chip mounting methods for semiconductor chips using Au bumps includes, for example,
(1) Au/Au direct bonding,
(2) Au/Au contact connection by chip adhesion with an insulative resin,
(3) Au/Ag grain/Au contact connection by chip adhesion with an anisotropically conductive resin,
(4) Au/Sn melt bonding.
In the contact connection system by resin adhesion (2) and (3), degradation is remarkable in various kinds of reliability tests after exposure to a high humidity circumstance and reliability is poor. In the melt bonding system using the low melting metal (4) and brittle intermetallic compounds are formed on the bonding boundary, tending to cause cracks in the course of cooling after bonding or during a temperature cycle test to lower the strength reliability. At present, a mounting method of most excellent reliability is the Au/Au direct bonding method.
In the existent technique of the Au/Au bonding system, a method of mounting a surface wave device formed with Au bumps in a face down manner on an Au pad of a wiring substrate by metal bonding under application of supersonic waves is disclosed as the prior art in Japanese Patent Laid-open Hei 10-107078 and in the technical report of Electronic Communication Society (July, 1995). In the prior art described above, for reliable metal bonding between an Au bump and an Au pad, the thickness of the Au pad is made 0.5 xcexcm or more and appropriate bonding conditions are adopted as follows: 75 to 300 gf/bump in bonding load; 150 to 250xc2x0 C. in bonding temperature; and 500 to 800 ms in supersonic wave application time. It is described that 40 to 100 gf/bump can be obtained as the shearing strength for the Au bump bonded portion under the conditions described above. Since the dielectric substrate of the surface wave device is made of a composite oxide system dielectric material, it is described that the device has extremely high strength and suffers from no damage by bonding up to a bonding load of 300 gf/bump. It is described that if the bonding conditions are less than the lower limit values thereof, that is, a bonding load of 75 gf/bump, a bonding temperature of 150xc2x0 C. and a supersonic wave application time of 300 ms, the bonding strength is lowered and the bonding becomes instable to result in unbonded parts or unbonded bumps thereby lowering the yield or deteriorating the connection reliability, making it difficult to assemble products. Further, only the ceramic substrate is described for the wiring substrate.
On the other hand, a method of mounting a semiconductor chip formed with Au bumps by metal bonding in a face down manner on a wiring substrate containing an organic material is disclosed as the prior art in Japanese Patent Laid-open Hei 10-275826. This prior art describes that a bonded pad portion coated with a hard metal: Ni (3-5 xcexcm)/Au (0.03-0.05 xcexcm) on the wiring substrate is cleaned before bonding by irradiation of ions or atoms in vacuum, and a chip used is stored in a non-oxidative atmosphere just after forming the bumps to keep the cleanness and they are bonded to each other. The wiring substrate and the chip are kept for a predetermined period of time in atmospheric air under heating and pressure and an alloy layer is formed between the hard metal and the Au bump to attain metal bonding. The appropriate bonding conditions are defined as 150 to 300xc2x0 C. in bonding temperature on the side of the chip and 60 to 120xc2x0 C. on the side of the substrate, 20 to 30 gf/bump in bonding load and 10 to 150 sec in bonding time. Au remains slightly on the surface of the pad after cleaning by the irradiation of ions or atoms and then bonding is conducted under the conditions described above to form an alloy layer between the hard film Ni and Au bump. It is described that they can be bonded so strongly as causing breakage in a state where a portion of the Ni layer is engraved and deposited to the top end of the bump electrode when the bonded portion is put to a rupture test. While it is described that the bonding temperature can be lowered and the bonding time can be shortened by applying supersonic waves, no details are shown.
Upon development of high speed and high function multi-chip modules mounting newest LSI chips, such as microcomputers, image processing devices and memories, we studied and evaluated the existent Au/Au bonding method. It was necessary for the module substrate to have a minimum wiring pitch of 90 to 40 xcexcm pitch in order to match it with the electrode pitch of the LSI chip. While the usual printed wiring substrate is manufactured by a method of appending a Cu foil and patterning the same by etching, the fine refined pitch is limited to about 100 xcexcm pitch. In the wiring substrate capable of coping with finer pitches, a build-up substrate formed by successive lamination system of forming a thin insulation film on a core substrate and then forming a pattern by a plating method is most promising in view of productivity, reliability and cost. However, the build-up substrate involves problems that the organic insulation layer formed by successive lamination has a relatively low glass transition temperature (100-150xc2x0 C.) and low modulus of elasticity and the plating processes is restricted to electroless plating making it difficult to form a thick plating layer in view of cost and that flip chip mounting by the existent Au/Au metal bonding is difficult since the rigidity of fine wiring is low due to the restriction in view of shape and size. Examples of our study made concretely are shown below.
A newest LSI chip was flip-chip mounted by Au/Au bonding on the build-up substrate described above by the supersonic bonding technique described above. As a result, under the conditions of 75 gf/bump in bonding load, 150 to 250xc2x0 C. in bonding temperature and 300 ms in bonding time, micro-cracks were formed on the insulation layer below Al electrodes of the chip formed with Au bumps and it was found that chip damage gives one of major problems in this mounting method. It was also found that fine wiring was deformed greatly when the build-up substrate was heated by the bonding load and the supersonic vibrations exerted on the fine wiring portion and cracks were formed in the Ni layer plated on the surface thereof to cause wiring disconnection. It was found that when the bonding load was lowered in order to avoid such problems, no sufficient bonding could be obtained and the initial conduction failure due to bonding failure could not be eliminated in the LSI chip of 50 pins or more and it is difficult to attain a bonding ratio of 100%. It was also found that an initial positional displacement of about 20 xcexcm at the maximum is caused in a chip of 10 mm square at a bonding temperature of 150xc2x0 C. due to the difference between a heat expansion coefficient of 17 ppm in the organic substrate and a heat expansion coefficient of 3 ppm in the LSI chip, and the positional displacement is promoted in the deformation process of the Au bumps during supersonic bonding tending to cause short circuit failure with respect to adjacent terminals. Further, when bonding was conducted on a pattern with coarse pitches, it was found that while position displacement or short circuit failure was not caused, large thermal strains were caused between the chip and the substrate in the cooling process after bonding to cause chip damage (cracks in the underlying insulation layer) in an LSI with thin Al thickness and weak underlying structure.
On the other hand, in the existent Au/Au bonding method of cleaning the surface of the substrate and then applying hot press bonding, when a newest LSI chip was flip-chip mounted on the build-up substrate having an Ni (5 xcexcm)/Au (0.05 xcexcm) specification, no sufficient metal bonding was attained by hot press bonding in atmospheric air under the conditions at a chip temperature of 150xc2x0 C. and a substrate temperature of 60xc2x0 C., for bonding times of 10 to 150 sec and at a bonding load of 20-30 gf/bump. The bonded state was evaluated by eroding the Al electrode of a bonded sample in an aqueous NaOH solution to remove a chip and checking the transfer rate of the Au bump to the substrate and the presence or absence of metal bonding was judged. As a result of the study on the bonding conditions capable of obtaining 100% Au bump transfer ratio, it was confirmed that a transfer ratio of 100% was obtained under the conditions at a chip temperature of 30xc2x0 C. and a substrate temperature of 120xc2x0 C. as the bonding temperature, at a bonding load of 10 to 30 gf/bump and for a bonding time of 150 sec or more. It was however found, since the bonding time is as long as 10 to 150 sec under any of the conditions described above, the temperature of the build-up substrate increased to lower the modulus of elasticity of the insulation layer laminated successively and, due to this phenomenon, a difference was caused to the extent of the deformation between the fine wiring portion of a region with Cu pattern wiring and the fine wiring portion of a region with no such Cu pattern wiring of the core substrate in the underlying portion. Then, it was found the deformation ratio of the Au bumps was scattered to form sufficient metal bonding for Au bumps with large deformation ratio but form no sufficient metal bonding for bumps with small deformation ratio. This is a problem not found in the existent printed wiring board constituted with materials of high glass transition temperature or high modulus of elasticity. While the metal bonding was attained also in the Au bumps with a small deformation ratio when the bonding temperature was increased since the bonding level was increased entirely, it was difficult to mount an LSI with a fine pitch of less than 100 xcexcm for the two reasons that the positional displacement between the bumps and the fine wiring was increased along with thermal expansion of the substrate and the fine wiring portion is deformed greatly to further induce positional displacement. Further, long bonding time results in increased production cost in view of productivity.
Further, a TEG chip simulating an LSI flip-chip mounted by way of an existent Au/Au bonding method to various wiring substrates and mounting samples filled with a resin incorporated with inorganic insulation filler having a heat expansion coefficient of about 30 ppm between the substrate and the chip was manufactured and evaluated by a temperature cycle test at xe2x88x9255/150xc2x0 C. It was found that, in the sample under the conditions where the transfer ratio of Au bumps to the substrate was 100%, the deformation of the Au bump was large to reduce the gap between the chip and the substrate to cause cracks between the Al electrode of the chip and the Au bumps and cause disconnection at a 1000 cycle level. It was found that, in the sample under the conditions of suppressing the deformation of the Au bumps, the transfer ratio of the Au bump did not reach 100% and, even with those confirmed for conduction at the initial stage, the bonding boundary between the Au bump and the Au connection terminal was opened to reach disconnection in a short period of time by a test for several hundred cycles.
It is an object of this invention to provide a method of manufacturing a semiconductor device by flip-chip connecting, by Au/Au metal bonding, an LSI chip having electrode pads with a minimum electrode pitch of 100 xcexcm or less and 50 pins or more, even all the pins, to an organic wiring board having a fine wiring layer with a minimum wiring pitch of 100 xcexcm or less and having a surface insulation layer with a low glass transition temperature, without causing positional displacement between the substrate and the chip, and without causing chip damage.
It is another object of this invention to provide a mounting structure as well as a mounting process with high assembling yield and excellent conductivity capable of mounting an LSI chip of multi-pin/fine pitch with high reliability and with low impedance characteristics to an organic wiring substrate having a fine wiring layer.
It is another object of this invention is to provide a semiconductor device in which a multi-pin LSI chip having electrode pads with 50 pins or more is mounted by flip-chip connection on an organic wiring substrate having, on a surface layer, a build-up layer comprising a fine wiring layer and an organic insulation layer with a low glass transition temperature, and in which the flip-chip connection portion is excellent in heat resistance, electrical characteristics, and high temperature/high humidity and temperature cycle reliability.
In this invention, to attain the first object described above, an Au bump is formed on an electrode of an LSI chip, the Au bump having a base of such a size that the diameter or one side of a rectangle thereof is 60 to 100% of an electrode size or 50 to 90% of the minimum electrode pitch with the height of 5 to 40 xcexcm, and a portion thereon of a size 70% or less of the diameter of the base which is further decreased toward the top end and the entire height from the bottom to the top being 30 xcexcm or more. On the other hand, an Au plating film is formed on the outermost surface of connection terminals of Cu wiring on the side of an organic wiring substrate having a fine wiring layer. Before flip-chip bonding them, the surface of the Au bump is physically etched by 5 nm or more by Ar ion sputtering under an atmospheric pressure or a reduced pressure of 0.1 to several Pa of Ar, while the Au plating surface on the side of the connection terminals is physically etched by 5 nm or more or by about {fraction (1/10)} to about xc2xd of the Au film thickness by Ar ion sputtering. In a case of physically etching both of them under the reduced pressure, the pressure is increased by a nitrogen gas or dry air removed with water content and they are taken out respectively into atmospheric air. An organic wiring substrate is mounted on a stage of a bonding apparatus, the LSI chip is upturned and adsorbed to a bonding tool surface of a supersonic bonding head, and both of them are positionally aligned and stacked to each other by lowering the bonding head. In this step, the stage or the bonding tool is kept at a predetermined temperature and the temperatures of the organic wiring substrate and the LSI chip are kept at a predetermined temperature in the positioning step. After stacking, pressure and supersonic vibrations are applied to the back of the chip to conduct metal bonding between the Au bump and the Au plating film. For the bonding conditions, the load P applied per 1 bump is selected from the range:
xc2xdS1(m2)xc3x97120(MPa)xe2x89xa6P(N)xe2x89xa6S1(m2)xc3x97180(MPa)xe2x80x83xe2x80x83(1) 
(where S1: Au bump/electrode contact area). That is under the load higher than the condition described above, chip damage caused by the deformation by the Au bump occurs at the contact portion between the Au bump and the chip electrode. On the other hand, under the lower load, the bonding area is remarkably decreased compared with the bump size and, when distortion occurs between the chip and the substrate, the bump main body is not deformed but strains are concentrated to the bonded boundary to increase the probability of wire disconnection.
Other bonding conditions are set to a humidity in the bonding atmosphere of 60% or less, a bonding temperature within a range from room temperature to 60xc2x0 C. on the side of the stage mounting the substrate and from room temperature to 150xc2x0 C. on the side of the bonding head, a bonding time within a range of 50 to 500 nm and a vibration amplitude in a case of 50 kHz within a range from 0.3 to 2.0 xcexcm for the amplitude of the chip. Accordingly, from 0.6 to 4.0 xcexcm in a case of the tool amplitude at the vibration transmission efficiency between the bonding tool and the chip of xc2xd, from which appropriate conditions are selected in accordance with a work. Further, the load is applied by a method of increasing from a low load to a high load during application of supersonic waves and the exposure time of the bonded work to atmospheric air from the surface cleaning to the bonding is 10 min or less. Under the range of the bonding conditions described above, it was confirmed that Au/Au metal bonding can be attained for all pins while retaining the deformation of the Au bumps only near the top end, with no positional displacement between the substrate and the chip and without causing damage to the chip. Examples for the result of the study are shown in FIGS. 12 and 13. FIG. 12 shows scanning electron microscopic images of the cross section and the tensile fracture surface of the bonded portions in a case of Ar-sputter cleaning for both surfaces of the organic substrate and the chip to about 20 nm in Au thickness and conducting supersonic bonding with a tool amplitude of 3 xcexcm. Even when the bonding area on the side of the substrate is decreased to about ⅕ compared with the bonding area on the side of the chip by decreasing the bonding load, it was confirmed that a portion of the bump is deposited on the side of the substrate in the tensile-fracture surface to provide metal bonding. The metal bonding defined herein means that bonding showing ductility rupture along with local elongation is attained in the Au/Au bonded portion in a case where it is fractured at the bonding boundary by tensile force. In addition, this can be confirmed by the observation of Au protrusions at the fractured surface observed on the side of the bump and on the side of the plating film along the broken cross section. FIG. 13 shows a cross sectional photograph in which chips with a bump size of 50 xcexcmxcfx86 and the electrode pitch of 80 xcexcm are bonded to a build-up substrate. Since the bonding temperature on the side of the substrate is at room temperature, there is no thermal deformation and it can be seen that the Au bump is bonded accurately about at the center of the connection terminal in view of the cross sectional images with a low magnification ratio. Furthermore, the state where the tissue of the Au bump is crushed flat only on the side of the substrate to provide metallic bonding can be seen from photographic images with a medium to high optical magnification ratio. When chip damage was checked for the bonded samples under the conditions described above, occurrence of damages was not observed. Based on the results of the study, it was confirmed that a method of manufacturing a semiconductor capable of reliably flip-chip bonding even an LSI chip having electrode pads with a minimum electrode pitch of 100 xcexcm or less and having 50 or more pins, and even all the pins, by Au/Au metal bonding without causing positional displacement between the substrate and the chip and without chip damage.
Then, to attain the second object, the Au bumps described above are formed to the LSI chip and the Au plating film is formed on the side of the substrate. The method of surface cleaning by sputtering before bonding adopts a step of simultaneously conducting an evacuation step and an Ar gas introduction step partially in which a step of mounting a plurality of LSI chips on a tray and conducting collective sputtering and a step of collectively sputtering a plurality of substrates are conducted successively in accordance with a required number of works. Further, a method of bonding by applying supersonic waves and a load while setting the bonding temperature to room temperature on the side of the stage for mounting the substrate and elevating the temperature only on the side of the bonding head for adsorption of the chip is adopted. At first, since the evacuation and Ar gas introduction are partially overlapped in view of the time in the sputter cleaning step, the time for controlling the Ar gas pressure to a predetermined pressure can be shortened to enable early starting for electric discharge. Since chips are handled in the tray, a plurality of chips can be transported and cleaned simultaneously. In addition, since the substrates and the chips are separately cleaned, the cleaning conditions for each of them can be optimized and required number of them can be cleaned respectively at good timing, so that time required for cleaning the work can be shortened greatly. Further, by the supersonic bonding combined with the step of cleaning the bonded surfaces of both of the substrate and the chip, Au/Au bondability can be improved greatly and bonding under low load, at low temperature and in short time is possible and the positioning step can be shortened since the temperature elevation time is shortened and the thermal fluctuation is not present, thereby greatly shortening the flip-chip bonding step to improve the productivity. Further, by the improvement of the bondability, bonding failure can be decreased drastically and the yield of the conductivity can be improved.
Then, to attain the third object, this invention adopts a structure in which a fine Cu wiring pattern on an organic insulation layer formed on a wiring substrate is formed in a shape protruding above the insulation layer, an Au film is formed on the outermost surface of the Cu wiring, metal bonding is conducted at such a bonding level that the Au bump bonded portion is elongated by 2 xcexcm or more relative to the tensile force for the Au bump on the LSI chip electrode and the Au plating layer, and a resin containing a fine inorganic filler with a low heat expansion coefficient is filled and cured in a gap between the chip and the substrate. Definition of the condition where Au is elongated by 2 xcexcm or more is shown together with fractured examples in FIGS. 9 to 11. Depending on the bonding level, the fractured position is classified into that near the bonding boundary of the bump/Au film, in the bump and near the bonding boundary of the bump/Al electrode. In each of the cases, Hb-H0 is defined as Au elongation. At first, since the structure connected by Au/Au metal bonding is adopted, the heat resistance and electrical characteristics of the connection portion can be improved greatly. Then, since the Au/Au bonding level has a performance capable of absorbing strains of 2 xcexcm or more in the bonding boundary, since the inorganic filler-incorporated resin is filled between the chip and the substrate, and cured so as not to exert large distortion on the bonded portion, and since the height of the wiring layer of the substrate is increased compared with the substrate surface to increase the substantial chip/substrate gap, thereby decreasing the thermal strain exerted on the bonded portion, the temperature cycle reliability can be improved remarkably and, since the extension of the chip/substrate gap by moisture absorption or the like can be absorbed by the ductile Au bonded portion, the high temperature/high humidity reliability can also be improved remarkably.